DCAN Registers
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23.4.39 IF2CMD Register (offset = 120h) [reset = 0h]
IF2CMD is shown in Figure 23-57 and described in Table 23-52.
The IF2 Command Register (IF1CMD) configures and initiates the transfer between the IF2 register sets
and the message RAM. It is configurable which portions of the message object should be transferred. A
transfer is started when the CPU writes the message number to bits [7:0] of the IF2 command register.
With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress.
After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be
completed and the Busy bit is cleared. The maximum number of cycles is needed when the message
transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the CPU
writes to both IF2 command registers consecutively (request of a second transfer while first transfer is still
in progress), the second transfer will start after the first one has been completed. While Busy bit is one,
IF2 register sets are write protected. For debug support, the auto clear functionality of the IF2 command
registers (clear of DMAactive flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message
Number is written to bits [7:0] of the IF2 command register, the message handler may access an
implemented (valid) message object instead.
Figure 23-57. IF2CMD Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
WR/RD Mask Arb Control ClrIntPnd TxRqst/NewDat Data_A Data_B
R/WP-0h R/WP-0h R/WP-0h R/WP-0h R/WP-0h R/WP-0h R/WP-0h R/WP-0h
15 14 13 12 11 10 9 8
Busy DMAactive Reserved
R/WP-0h R/WP-0h R-0h
7 6 5 4 3 2 1 0
Message_Number
R/WP-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-52. IF2CMD Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R 0h
23 WR/RD R/WP 0h
Write/Read
0x0 = Direction = Read: Transfer direction is from the message
object addressed by Message Number (Bits [7:0]) to the IF2 register
set.
0x1 = Direction = Write: Transfer direction is from the IF2 register set
to the message object addressed by Message Number (Bits [7:0]).
22 Mask R/WP 0h
Access mask bits
0x0 = Mask bits will not be changed
0x1 = Direction = Read: The mask bits (identifier mask + MDir +
MXtd) will be transferred from the message object addressed by
Message Number (Bits [7:0]) to the IF2 register set. Direction =
Write: The mask bits (identifier mask + MDir + MXtd) will be
transferred from the IF2 register set to the message object
addressed by Message Number (Bits [7:0]).
21 Arb R/WP 0h
Access arbitration bits
0x0 = Arbitration bits will not be changed
0x1 = Direction = Read: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the message object addressed by
Message Number (Bits [7:0]) to the corresponding IF2 register set.
Direction = Write: The Arbitration bits (Identifier + Dir + Xtd +
MsgVal) will be transferred from the IF2 register set to the message
object addressed by Message Number (Bits [7:0]).
3968
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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