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DMTimer 1ms
20.2.5.3 TISTAT Register (offset = 14h) [reset = 0h]
TISTAT is shown in Figure 20-37 and described in Table 20-38.
This register provides status information about the module, excluding the interrupt status information
Figure 20-37. TISTAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved ResetDone
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-38. TISTAT Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
Reads return 0 Reserved for OCP-socket status information
0 ResetDone R 0h
Internal reset monitoring
0 = rstongoing : Internal module reset in on-going
1 = rstcomp : Reset completed
3601
SPRUH73H–October 2011–Revised April 2013 Timers
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