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Table 21-3. I2C(1–2) Connectivity Attributes
Attributes Type
Power Domain Peripheral Domain
Clock Domain PD_PER_L4LS_GCLK (Interface/OCP)
PD_PER_I2C_FCLK (Func)
Reset Signals PER_DOM_RST_N
Idle/Wakeup Signals Smart Idle
Interrupt Requests 1 interrupt per instance to MPU Subsystem (I2C1INT, I2C2INT)
DMA Requests 2 DMA requests per instance to EDMA (I2CTXEVTx,
I2CRXEVTx)
Physical Address L4 Peripheral slave port
21.2.2 I2C Clock and Reset Management
The I2C controllers have separate bus interface and functional clocks. During power-down mode, the
I2Cx_SCL and I2Cx_SDA are configured as inputs.
Table 21-4. I2C Clock Signals
Clock Signal Max Freq Reference / Source Comments
I2C0 Clock Signals
PIOCPCLK 100 MHz CORE_CLKOUTM4 / 2 pd_wkup_l4_wkup_gclk
Interface clock From PRCM
PISYSCLK 48 MHz PER_CLKOUTM2 / 4 pd_wkup_i2c0_gfclk
Functional clock From PRCM
I2C(1-2) Clock Signals
PIOCPCLK 100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk
Interface clock From PRCM
PISYSCLK 48 MHz PER_CLKOUTM2 / 4 pd_per_ic2_fclk
Functional clock From PRCM
21.2.3 I2C Pin List
The external signals (I2Cx_SDA, I2Cx_SCL) on the device use standard LVCMOS I/Os and may not meet
full compliance with the I2C specifications for Fast-mode devices for slope control and input filtering (spike
suppression) to improve the EMC behavior.
Table 21-5. I2C Pin List
Pin Type Description
I2Cx_SCL I/OD
(1)
I2C serial clock (open drain)
I2Cx_SDA I/OD I2C serial data (open drain)
(1)
This
output
signal
is
also
used
as
a
retiming
input.
The
associated
CONF_<module>_<pin>_RXACTIVE
bit
for
the
output
clock
must be set to 1 to enable the clock input back to the module.
3701
SPRUH73H–October 2011–Revised April 2013 I2C
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