Ethernet Subsystem Registers
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14.5.9.2 SOFT_RESET Register (offset = 4h) [reset = 0h]
SOFT_RESET is shown in Figure 14-198 and described in Table 14-216.
SUBSYSTEM SOFT RESET REGISTER
Figure 14-198. SOFT_RESET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved SOFT_RESET
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-216. SOFT_RESET Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 SOFT_RESET R/W 0h Software reset - Writing a one to this bit causes the CPGMACSS_R
logic to be reset (INT, REGS, CPPI).
Software reset occurs on the clock following the register bit write.
1440
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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