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CONTROL_MODULE Registers
9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h]
init_priority_0 is shown in Figure 9-20 and described in Table 9-27.
Figure 9-20. init_priority_0 Register
31 30 29 28 27 26 25 24
Reserved tcwr2 tcrd2
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
tcwr1 tcrd1 tcwr0 tcrd0
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
p1500 Reserved
R/W-0h R-0h
7 6 5 4 3 2 1 0
mmu pru_icss Reserved host_arm
R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-27. init_priority_0 Register Field Descriptions
Bit Field Type Reset Description
31-28 Reserved R 0h
27-26 tcwr2 R/W 0h TPTC 2 Write Port initiator priority
25-24 tcrd2 R/W 0h TPTC 2 Read Port initiator priority
23-22 tcwr1 R/W 0h TPTC 1 Write Port initiator priority
21-20 tcrd1 R/W 0h TPTC 1 Read Port initiator priority
19-18 tcwr0 R/W 0h TPTC 0 Write Port initiator priority
17-16 tcrd0 R/W 0h TPTC 0 Read Port initiator priority
15-14 p1500 R/W 0h P1500 Port Initiator priority
13-8 Reserved R 0h
7-6 mmu R/W 0h System MMU initiator priority
5-4 pru_icss R/W 0h PRU-ICSS initiator priority
3-2 Reserved R 0h
1-0 host_arm R/W 0h Host Cortex A8 initiator priority
779
SPRUH73H–October 2011–Revised April 2013 Control Module
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