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LCD Registers
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h]
CLKC_ENABLE is shown in Figure 13-44 and described in Table 13-39.
Figure 13-44. CLKC_ENABLE Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved dma_clk_en lidd_clk_en core_clk_en
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 13-39. CLKC_ENABLE Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 dma_clk_en R/W 0h Software Clock Enable for the DMA submodule
The DMA submodule runs on the L3 Clock domain
1 lidd_clk_en R/W 0h Software Clock Enable for the LIDD submodule (character displays)
The LIDD submodule runs on the System Clock (lcd_clk) domain
0 core_clk_en R/W 0h Software Clock Enable for the Core, which encompasses the Raster
Active Matrix and Passive Matrix logic
The Core runs on the System Clock (lcd_clk) domain
1161
SPRUH73H–October 2011–Revised April 2013 LCD Controller
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