Power, Reset, and Clock Management
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8.1.13.2.3 PM_PER_PWRSTCTRL Register (offset = Ch) [reset = EE0000EBh]
PM_PER_PWRSTCTRL is shown in Figure 8-171 and described in Table 8-187.
Controls the power state of PER power domain
Figure 8-171. PM_PER_PWRSTCTRL Register
31 30 29 28 27 26 25 24
ram_mem_ONState PER_mem_RETState Reserved ram_mem_RETState PER_mem_ONState Reserved
R/W-3h R/W-1h R-0h R/W-1h R/W-3h R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
pru_icss_mem_RETSt pru_icss_mem_ONState LowPowerStateChang LogicRETState Reserved PowerState
ate e
R/W-1h R/W-3h R/W-0h R/W-1h R-0h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-187. PM_PER_PWRSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-30 ram_mem_ONState R/W 3h
OCMC RAM memory on state
0x0 = OFF : Memory is OFF
0x1 = RET : Memory is in retention state
0x2 = RESERVED
0x3 = ON : Memory is ON
29 PER_mem_RETState R/W 1h
Other memories in PER Domain RET state
0x0 = OFF
0x1 = RET
28 Reserved R 0h
27 ram_mem_RETState R/W 1h
OCMC RAM memory RET state
0x0 = OFF : Memory is in off state
0x1 = RET : Memory is in retention state
26-25 PER_mem_ONState R/W 3h
Other memories in PER Domain ON state
0x0 = Reserved2
0x1 = Reserved1
0x2 = Reserved : Reserved
0x3 = ON : Memory is ON
24-8 Reserved R 0h
7 pru_icss_mem_RETState R/W 1h
PRU-ICSS memory RET state
0x0 = OFF : Memory is in off state
0x1 = RET : Memory is in retention state
6-5 pru_icss_mem_ONState R/W 3h
PRU-ICSS memory ON state
0x0 = Reserved2
0x1 = Reserved1
0x2 = Reserved : Reserved
0x3 = ON : Memory is ON
714
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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