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CONTROL_MODULE Registers
9.3.13 deepsleep_ctrl Register (offset = 470h) [reset = 0h]
deepsleep_ctrl is shown in Figure 9-16 and described in Table 9-23.
Figure 9-16. deepsleep_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved dsenable Reserved
R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8
dscount
R/W-0h
7 6 5 4 3 2 1 0
dscount
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-23. deepsleep_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-18 Reserved R 0h
17 dsenable R/W 0h Deep sleep enable
0: Normal operation
1: Master oscillator output is gated
16 Reserved R 0h
15-0 dscount R/W 0h Programmable count of how many CLK_M_OSC clocks needs to be
seen before exiting deep sleep mode
775
SPRUH73H–October 2011–Revised April 2013 Control Module
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