USB Registers
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16.5.4.9 BIST Register (offset = 24h) [reset = 0h]
BIST is shown in Figure 16-142 and described in Table 16-153.
COntains bits related to the built in self test of the phy
Figure 16-142. BIST Register
31 30 29 28 27 26 25 24
BIST_START REDUCED_SWING BIST_CRC_CALC_E BIST_PKT_LENGTH
N
R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
BIST_PKT_LENGTH LOOPBACK_EN BIST_OP_PHASE_SEL
R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
SWEEP_EN SWEEP_MODE BIST_PASS BIST_BUSY Reserved
R/W-0h R/W-0h R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved OP_CODE RX_TEST_MODE Reserved INTER_PKT_DELAY_ HS_ALL_ONES_TES USE_BIST_TX_PHAS
TEST T ES
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-153. BIST Register Field Descriptions
Bit Field Type Reset Description
31 BIST_START R/W 0h
When set to 1 the BIST mode is started.
30 REDUCED_SWING R/W 0h
When 1 the TX swing is reduced in BIST mode
29 BIST_CRC_CALC_EN R/W 0h
Enables CRC calculation during BIST when set to 1
28-20 BIST_PKT_LENGTH R/W 0h
Address for which BIST to select
19 LOOPBACK_EN R/W 0h
Enables the loopback mode
18-16 BIST_OP_PHASE_SEL R/W 0h
Selects which phase to use for data transmission during BIST
15 SWEEP_EN R/W 0h
Enables freq sweep on CDR
14-12 SWEEP_MODE R/W 0h Selects the freq sweep mode.
Details in DFT spec.
11 BIST_PASS R 0h Indicates that the BIST has passed.
Read value is valid only if VDDLDO is on.
10 BIST_BUSY R 0h Indicates that BIST is running.
Read value is valid only if VDDLDO is on.
9-7 Reserved R/W 0h
6-5 OP_CODE R/W 0h
Defined in DFT spec
4 RX_TEST_MODE R/W 0h
Defined in DFT spec
3 Reserved R/W 0h
2 INTER_PKT_DELAY_TES R/W 0h
Defined in DFT spec
T
1 HS_ALL_ONES_TEST R/W 0h
Defined in DFT spec
0 USE_BIST_TX_PHASES R/W 0h When set to 1 bits
18-16 are activated for choosing the transmitting phase.
1914
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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