Power, Reset, and Clock Management
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8.1.13.3.1 RM_WKUP_RSTCTRL Register (offset = 0h) [reset = 8h]
RM_WKUP_RSTCTRL is shown in Figure 8-172 and described in Table 8-189.
This register controls the release of the ALWAYS ON Domain resets.
Figure 8-172. RM_WKUP_RSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved WKUP_M3_LRST Reserved
R-0h R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-189. RM_WKUP_RSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-4 Reserved R 0h
3 WKUP_M3_LRST R/W 1h
Assert Reset to WKUP_M3
0x0 = CLEAR : Reset is cleared for the M3
0x1 = ASSERT : Reset is asserted for the M3 by A8
2-0 Reserved R 0h
716
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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