Mailbox
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Table 17-2. Mailbox Clock Signals
Clock Signal Max Freq Reference / Source Comments
Functional / Interface clock 100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk
From PRCM
17.1.2.3 Mailbox Pin List
The Mailbox module does not include any external interface pins.
17.1.3 Functional Description
This device has the following mailbox instances:
• System mailbox
Table 17-3 shows Mailbox Implementation in this device, where u is the user number and m is the mailbox
number.
Table 17-3. Mailbox Implementation
Mailbox Type User Number(u) Mailbox Number(m) Messages per Mailbox
System mailbox 0 to 3 0 to 7 4
The mailbox module provides a means of communication through message queues among the users
(depending on the mailbox module instance). The individual mailbox modules (8 for the system mailbox
instance), or FIFOs, can associate (or de-associate) with any of the processors using the
MAILBOX_IRQENABLE_SET_u (or MAILBOX_IRQENABLE_CLR_u) register.
The system mailbox module includes the following user subsystems:
• User 0: MPU Subsystem (u = 0)
• User 1: PRU_ICSS PRU0 (u = 1)
• User 2: PRU_ICSS PRU1 (u = 2)
• User 3: WakeM3 (u = 3)
Each user has a dedicated interrupt signal from the corresponding mailbox module instance and dedicated
interrupt enabling and status registers. Each
MAILBOX_IRQSTATUS_RAW_u/MAILBOX_IRQSTATUS_CLR_u interrupt status register corresponds to
a particular user.
For the system mailbox instance, a user can query its interrupt status register through the L4_STANDARD
interconnect.
17.1.3.1 Mailbox Block Diagram
Figure 17-2 shows the mailbox block diagram.
3238
Interprocessor Communication SPRUH73H–October 2011–Revised April 2013
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