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CONTROL_MODULE Registers
9.3.63 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h]
tpcc_evt_mux_28_31 is shown in Figure 9-66 and described in Table 9-73.
Figure 9-66. tpcc_evt_mux_28_31 Register
31 30 29 28 27 26 25 24
Reserved evt_mux_31
R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved evt_mux_30
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved evt_mux_29
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved evt_mux_28
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-73. tpcc_evt_mux_28_31 Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29-24 evt_mux_31 R/W 0h Selects 1 of 64 inputs for DMA event 31
23-22 Reserved R 0h
21-16 evt_mux_30 R/W 0h Selects 1 of 64 inputs for DMA event 30
15-14 Reserved R 0h
13-8 evt_mux_29 R/W 0h Selects 1 of 64 inputs for DMA event 29
7-6 Reserved R 0h
5-0 evt_mux_28 R/W 0h Selects 1 of 64 inputs for DMA event 28
827
SPRUH73H–October 2011–Revised April 2013 Control Module
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