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EDMA3 Registers

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11.4.1.6.3 Event Set Registers (ESR, ESRH)

The event set registers (ESR/ESRH) allow the CPU (EDMA3 programmers) to manually set events to

initiate DMA transfer requests. CPU writes of 1 to any event set register (En) bits set the corresponding

bits in the registers. The set event is evaluated by the EDMA3CC logic for an associated transfer request

submission to the transfer controllers. Writing a 0 has no effect.

The event set registers operate independent of the event registers (ER/ERH), and a write of 1 is always

considered a valid event regardless of whether the event is enabled (the corresponding event bits are set

or cleared in EER.En/EERH.En).

Once the event is set in the event set registers, it cannot be cleared by CPU writes, in other words, the

event clear registers (ECR/ECRH) have no effect on the state of ESR/ESRH. The bits will only be cleared

once the transfer request corresponding to the event has been submitted to the transfer controller. The

setting of an event is a higher priority relative to clear operations (via hardware). If set and clear conditions

occur concurrently, the set condition wins. If the event was previously set, then EMR/EMRH would be set

because an event is lost. If the event was previously clear, then the event remains set and is prioritized for

submission to the event queues.

Manually-triggered transfers via writes to ESR/ESRH allow the CPU to submit DMA requests in the

system, these are relevant for memory-to-memory transfer scenarios. If the ESR.En/ESRH.En bit is

already set and another CPU write of 1 is attempted to the same bit, then the corresponding event is

latched in the event missed registers (EMR.En/EMRH.En = 1).

The ESR is shown in Figure 11-74 and described in Table 11-58. The ESRH is shown in Figure 11-75 and

described in Table 11-59.

Figure 11-74. Event Set Register (ESR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 11-58. Event Set Register (ESR) Field Descriptions

Bit Field Value Description

31-0 En Event set for event 0-31.

0 No effect.

1 Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the

EDMA3TC.

972

Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013

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