Ethernet Subsystem Registers
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14.5.6.40 P2_TX_PRI_MAP Register (offset = 218h) [reset = 33221001h]
P2_TX_PRI_MAP is shown in Figure 14-160 and described in Table 14-175.
CPSW PORT 2 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER
Figure 14-160. P2_TX_PRI_MAP Register
31 30 29 28 27 26 25 24
Reserved PRI7 Reserved PRI6
R/W-3h R/W-3h
23 22 21 20 19 18 17 16
Reserved PRI5 Reserved PRI4
R/W-2h R/W-2h
15 14 13 12 11 10 9 8
Reserved PRI3 Reserved PRI2
R/W-1h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI1 Reserved PRI0
R/W-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-175. P2_TX_PRI_MAP Register Field Descriptions
Bit Field Type Reset Description
29-28 PRI7 R/W 3h Priority
7 - A packet header priority of 0x7 is given this switch queue pri.
25-24 PRI6 R/W 3h Priority
6 - A packet header priority of 0x6 is given this switch queue pri.
21-20 PRI5 R/W 2h Priority
5 - A packet header priority of 0x5 is given this switch queue pri.
17-16 PRI4 R/W 2h Priority
4 - A packet header priority of 0x4 is given this switch queue pri.
13-12 PRI3 R/W 1h Priority
3 - A packet header priority of 0x3 is given this switch queue pri.
9-8 PRI2 R/W 0h Priority
2 - A packet header priority of 0x2 is given this switch queue pri.
5-4 PRI1 R/W 0h Priority
1 - A packet header priority of 0x1 is given this switch queue pri.
1-0 PRI0 R/W 1h Priority
0 - A packet header priority of 0x0 is given this switch queue pri.
1398
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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