Enhanced PWM (ePWM) Module
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15.2.4.1 Time-Base Submodule Registers
Table 15-59 lists the memory-mapped registers for the time-base submodule. All other register offset
addresses not listed in Table 15-59 should be considered as reserved locations and the register contents
should not be modified.
Table 15-59. Time-Base Submodule Registers
Offset Acronym Register Description Section
0h TBCTL Time-Base Control Register Section 15.2.4.1.1
2h TBSTS Time-Base Status Register Section 15.2.4.1.2
4h TBPHSHR Time-Base Phase High-Resolution Register
(1)
Section 15.2.4.8.1
6h TBPHS Time-Base Phase Register Section 15.2.4.1.3
8h TBCNT Time-Base Counter Register Section 15.2.4.1.4
Ah TBPRD Time-Base Period Register Section 15.2.4.1.5
(1)
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved.
15.2.4.1.1 Time-Base Control Register (TBCTL)
The time-base control register (TBCTL) is shown in Figure 15-70 and described in Table 15-60.
Figure 15-70. Time-Base Control Register (TBCTL)
15 14 13 12 10 9 8
FREE, SOFT PHSDIR CLKDIV HSPCLKDIV
R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-60. Time-Base Control Register (TBCTL) Field Descriptions
Bit Field Value Description
15-14 FREE, SOFT 0-3h Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
0 Stop after the next time-base counter increment or decrement
1h Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCNT = TBPRD)
• Down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
• Up-down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
2h-3h Free run
13 PHSDIR Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-
count mode. The PHSDIR bit indicates the direction the time-base counter (TBCNT) will count after
a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register.
This is irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
0 Count down after the synchronization event.
1 Count up after the synchronization event.
1582
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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