GPIO Registers
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25.4 GPIO Registers
25.4.1 GPIO Registers
Table 25-5 lists the memory-mapped registers for the GPIO. All register offset addresses not listed in
Table 25-5 should be considered as reserved locations and the register contents should not be modified.
Table 25-5. GPIO REGISTERS
Offset Acronym Register Name Section
0h GPIO_REVISION Section 25.4.1.1
10h GPIO_SYSCONFIG Section 25.4.1.2
20h GPIO_EOI Section 25.4.1.3
24h GPIO_IRQSTATUS_RAW_0 Section 25.4.1.4
28h GPIO_IRQSTATUS_RAW_1 Section 25.4.1.5
2Ch GPIO_IRQSTATUS_0 Section 25.4.1.6
30h GPIO_IRQSTATUS_1 Section 25.4.1.7
34h GPIO_IRQSTATUS_SET_0 Section 25.4.1.8
38h GPIO_IRQSTATUS_SET_1 Section 25.4.1.9
3Ch GPIO_IRQSTATUS_CLR_0 Section 25.4.1.10
40h GPIO_IRQSTATUS_CLR_1 Section 25.4.1.11
44h GPIO_IRQWAKEN_0 Section 25.4.1.12
48h GPIO_IRQWAKEN_1 Section 25.4.1.13
114h GPIO_SYSSTATUS Section 25.4.1.14
130h GPIO_CTRL Section 25.4.1.15
134h GPIO_OE Section 25.4.1.16
138h GPIO_DATAIN Section 25.4.1.17
13Ch GPIO_DATAOUT Section 25.4.1.18
140h GPIO_LEVELDETECT0 Section 25.4.1.19
144h GPIO_LEVELDETECT1 Section 25.4.1.20
148h GPIO_RISINGDETECT Section 25.4.1.21
14Ch GPIO_FALLINGDETECT Section 25.4.1.22
150h GPIO_DEBOUNCENABLE Section 25.4.1.23
154h GPIO_DEBOUNCINGTIME Section 25.4.1.24
190h GPIO_CLEARDATAOUT Section 25.4.1.25
194h GPIO_SETDATAOUT Section 25.4.1.26
4068
General-Purpose Input/Output SPRUH73H–October 2011–Revised April 2013
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