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CONTROL_MODULE Registers
9.3.55 vref_ctrl Register (offset = E14h) [reset = 0h]
vref_ctrl is shown in Figure 9-58 and described in Table 9-65.
Figure 9-58. vref_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved ddr_vref_ccap ddr_vref_tap ddr_vref_en
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-65. vref_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-5 Reserved R 0h
4-3 ddr_vref_ccap R/W 0h select for coupling cap for DDR
00 : No capacitor connected
01 : Capacitor between BIAS2 and VSS
10 : Capacitor between BIAS2 and VDDS
11: Capacitor between BIAS2 and VSS andamp
Capacitor between BIAS2 and VDDS
2-1 ddr_vref_tap R/W 0h select for int ref for DDR
00 : Pad/Bias2 connected to internal reference VDDS/2 for 2uA
current load
01 : Pad/Bias2 connected to internal reference VDDS/2 for 4uA
current load
10 : Pad/Bias2 connected to internal reference VDDS/2 for 6uA
current load
11 : Pad/Bias2 connected to internal reference VDDS/2 for 8uA
current load
0 ddr_vref_en R/W 0h active high internal reference enable for DDR
819
SPRUH73H–October 2011–Revised April 2013 Control Module
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