Ethernet Subsystem Registers
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14.5.7.11 TX_GAP Register (offset = 28h) [reset = Ch]
TX_GAP is shown in Figure 14-183 and described in Table 14-199.
TRANSMIT INTER-PACKET GAP REGISTER
Figure 14-183. TX_GAP Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved TX_GAP
R-0h R/W-Ch
7 6 5 4 3 2 1 0
TX_GAP
R/W-Ch
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-199. TX_GAP Register Field Descriptions
Bit Field Type Reset Description
31-9 Reserved R 0h
8-0 TX_GAP R/W Ch
Transmit Inter-Packet Gap
14.5.8 CPSW_SS Registers
Table 14-200 lists the memory-mapped registers for the CPSW_SS. All register offset addresses not listed
in Table 14-200 should be considered as reserved locations and the register contents should not be
modified.
Table 14-200. CPSW_SS REGISTERS
Offset Acronym Register Name Section
0h ID_VER ID VERSION REGISTER Section 14.5.8.1
4h CONTROL SWITCH CONTROL REGISTER Section 14.5.8.2
8h SOFT_RESET SOFT RESET REGISTER Section 14.5.8.3
Ch STAT_PORT_EN STATISTICS PORT ENABLE REGISTER Section 14.5.8.4
10h PTYPE TRANSMIT PRIORITY TYPE REGISTER Section 14.5.8.5
14h SOFT_IDLE SOFTWARE IDLE Section 14.5.8.6
18h THRU_RATE THROUGHPUT RATE Section 14.5.8.7
1Ch GAP_THRESH CPGMAC_SL SHORT GAP THRESHOLD Section 14.5.8.8
20h TX_START_WDS TRANSMIT START WORDS Section 14.5.8.9
24h FLOW_CONTROL FLOW CONTROL Section 14.5.8.10
28h VLAN_LTYPE LTYPE1 AND LTYPE 2 REGISTER Section 14.5.8.11
2Ch TS_LTYPE VLAN_LTYPE1 AND VLAN_LTYPE2 REGISTER Section 14.5.8.12
30h DLR_LTYPE DLR LTYPE REGISTER Section 14.5.8.13
1424
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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