UART Registers
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19.5.1.5 Interrupt Enable Register (IER) - CIR Mode
The CIR interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 5
types of interrupt in these modes, TX status, RX overrun, RX stop interrupt, THR interrupt, and RHR
interrupt. Each interrupt can be enabled/disabled individually. The CIR interrupt enable register (IER) is
shown in Figure 19-38 and described in Table 19-34.
NOTE: In CIR mode, the TXSTATUSIT bit has only one meaning corresponding to the case
MDR2[0] = 0.
The RXSTOPIT interrupt is generated based on the value set in the BOF Length register
(EBLR).
Figure 19-38. CIR Interrupt Enable Register (IER)
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved TXSTATUSIT Reserved RXOVERRUNIT RXSTOPIT THRIT RHRIT
R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-34. CIR Interrupt Enable Register (IER) Field Descriptions
Bit Field Value Description
15-6 Reserved 0 Reserved.
5 TXSTATUSIT 0 Disables the TX status interrupt.
1 Enables the TX status interrupt.
4 Reserved 0 Reserved.
3 RXOVERRUNIT 0 Disables the RX overrun interrupt.
1 Enables the RX overrun interrupt.
2 RXSTOPIT 0 Disables the RX stop interrupt.
1 Enables the RX stop interrupt.
1 THRIT 0 Disables the THR interrupt.
1 Enables the THR interrupt.
0 RHRIT 0 Disables the RHR interrupt.
1 Enables the RHR interrupt.
3510
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
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