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Touchscreen Controller Registers
12.5.1.11 ADCSTAT Register (offset = 44h) [reset = 10h]
ADCSTAT is shown in Figure 12-15 and described in Table 12-15.
General Status bits @TSC_ADC_SS_Sequencer_Status Register
Figure 12-15. ADCSTAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
PEN_IRQ1 PEN_IRQ0 FSM_BUSY STEP_ID
R-0h R-0h R-0h R-10h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-15. ADCSTAT Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
-
7 PEN_IRQ1 R 0h
PEN_IRQ[1] status
6 PEN_IRQ0 R 0h
PEN_IRQ[0] status
5 FSM_BUSY R 0h Status of OCP FSM and ADC FSM.
0 = Idle.
1 = Busy.
4-0 STEP_ID R 10h Encoded values:.
10000 = Idle.
10001 = Charge.
00000 = Step 1.
00001 = Step 2.
00010 = Step 3.
00011 = Step 4.
00100 = Step 5.
00101 = Step 6.
00110 = Step 7.
00111 = Step 8.
01000 = Step 9.
01001 = Step 10.
01010 = Step 11.
01011 = Step 12.
01100 = Step 13.
01101 = Step 14.
01110 = Step 15.
01111 = Step 16.
1049
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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