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USB Registers
16.5.6.2 WORDx Register (offset = 800h to 900h) [reset = 0h]
WORD0 to WORD63 is shown in Figure 16-276 and described in Table 16-289.
Figure 16-276. WORD0 to WORD63 Register
31 30 29 28 27 26 25 24
ENTRY3_RXTX Reserved ENTRY3_CHANNEL
W-0h R/W-
23 22 21 20 19 18 17 16
ENTRY2_RXTX Reserved ENTRY2_CHANNEL
W-0h R/W-
15 14 13 12 11 10 9 8
ENTRY1_RXTX Reserved ENTRY1_CHANNEL
W-0h R/W-
7 6 5 4 3 2 1 0
ENTRY0_RXTX Reserved ENTRY0_CHANNEL
W-0h R/W-
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-289. WORD0 to WORD63 Register Field Descriptions
Bit Field Type Reset Description
31 ENTRY3_RXTX W 0h This bit indicates if this entry is for a Tx or an Rx channel and is
encoded as follows:
0 = Tx Channel
1 = Rx Channel
28-24 ENTRY3_CHANNEL R/W This field indicates the channel number that is to be given an
opportunity to transfer data.
If this is a Tx entry, the DMA will be presented with a scheduling
credit for that exact Tx channel.
If this is an Rx entry, the DMA will be presented with a scheduling
credit for the Rx FIFO that is associated with this channel.
For Rx FIFOs which carry traffic for more than 1 Rx DMA channel,
the exact channel number that is given in the Rx credit will actually
be the channel number which is currently on the head element of
that Rx FIFO, which is not necessarily the channel number given in
the scheduler table entry.
23 ENTRY2_RXTX W 0h This bit indicates if this entry is for a Tx or an Rx channel and is
encoded as follows:
0 = Tx Channel
1 = Rx Channel
20-16 ENTRY2_CHANNEL R/W This field indicates the channel number that is to be given an
opportunity to transfer data.
If this is a Tx entry, the DMA will be presented with a scheduling
credit for that exact Tx channel.
If this is an Rx entry, the DMA will be presented with a scheduling
credit for the Rx FIFO that is associated with this channel.
For Rx FIFOs which carry traffic for more than 1 Rx DMA channel,
the exact channel number that is given in the Rx credit will actually
be the channel number which is currently on the head element of
that Rx FIFO, which is not necessarily the channel number given in
the scheduler table entry.
15 ENTRY1_RXTX W 0h This bit indicates if this entry is for a Tx or an Rx channel and is
encoded as follows:
0 = Tx Channel
1 = Rx Channel
2083
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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