www.ti.com
DMTimer 1ms
20.2.5.15 TCAR2 Register (offset = 44h) [reset = 0h]
TCAR2 is shown in Figure 20-49 and described in Table 20-50.
This register holds the value of the second counter register capture
Figure 20-49. TCAR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPTURE_VALUE2
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-50. TCAR2 Register Field Descriptions
Bit Field Type Reset Description
31-0 CAPTURE_VALUE2 R 0h
The value of second captured counter register
3615
SPRUH73H–October 2011–Revised April 2013 Timers
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
