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GPMC
7.1.5.29 GPMC_BCH_RESULT0_i
Figure 7-79. GPMC_BCH_RESULT0_i
31 0
BCH_RESULT0_i
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-83. GPMC_BCH_RESULT0_i Field Descriptions
Bit Field Value Description
31-0 BCH_RESULT0_i 0-FFFF FFFFh BCH ECC result, bits 0 to 31
7.1.5.30 GPMC_BCH_RESULT1_i
Figure 7-80. GPMC_BCH_RESULT1_i
31 0
BCH_RESULT1_i
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-84. GPMC_BCH_RESULT1_i Field Descriptions
Bit Field Value Description
31-0 BCH_RESULT1_i 0-FFFF FFFFh BCH ECC result, bits 32 to 63
7.1.5.31 GPMC_BCH_RESULT2_i
Figure 7-81. GPMC_BCH_RESULT2_i
31 0
BCH_RESULT2_i
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-85. GPMC_BCH_RESULT2_i Field Descriptions
Bit Field Value Description
31-0 BCH_RESULT2_i 0-FFFF FFFFh BCH ECC result, bits 64 to 95
395
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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