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Ethernet Subsystem Registers
14.5.2.24 CPDMA_IN_VECTOR Register (offset = 90h) [reset = 0h]
CPDMA_IN_VECTOR is shown in Figure 14-52 and described in Table 14-63.
CPDMA_INT INPUT VECTOR (READ ONLY)
Figure 14-52. CPDMA_IN_VECTOR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_IN_VECTOR
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-63. CPDMA_IN_VECTOR Register Field Descriptions
Bit Field Type Reset Description
31-0 DMA_IN_VECTOR R 0h DMA Input Vector - The value of DMA_In_Vector is reset to zero, but
will change to the IN_VECTOR bus value one clock after reset is
deasserted.
Thereafter, this value will change to a new IN_VECTOR value one
clock after the IN_VECTOR value changes.
1283
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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