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Pulse-Width Modulation Subsystem (PWMSS)
15.1.3.4 CLKSTATUS Register (offset = Ch) [reset = 0h]
CLKSTATUS is shown in Figure 15-5 and described in Table 15-9.
The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status.
Figure 15-5. CLKSTATUS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved ePWM_CLKSTOP_A ePWM_CLK_EN_ACK
CK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved eQEP_CLKSTOP_AC eQEP_CLK_EN_ACK Reserved eCAP_CLKSTOP_AC eCAP_CLK_EN_ACK
K K
R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-9. CLKSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9 ePWM_CLKSTOP_ACK R 0h
This bit is the clkstop_req_ack status output of the ePWM module.
8 ePWM_CLK_EN_ACK R 0h
This bit is the clk_en status output of the ePWM module.
7-6 Reserved R 0h
5 eQEP_CLKSTOP_ACK R 0h
This bit is the clkstop_req_ack status output of the eQEP module.
4 eQEP_CLK_EN_ACK R 0h
This bit is the clk_en status output of the eQEP module.
3-2 Reserved R 0h
1 eCAP_CLKSTOP_ACK R 0h
This bit is the clkstop_req_ack status output of the eCAP module.
0 eCAP_CLK_EN_ACK R 0h
This bit is the clk_en status output of the eCAP module.
1493
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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