GPMC
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7.1.5 Registers
Table 7-54 provides a summary of the GPMC registers. All GPMC registers are aligned to 32-bit address
boundaries. All register file accesses, except the GPMC_NAND_DATA_i register, are little-endian. If the
GPMC_NAND_DATA_i register is accessed, the endianness is access-dependent.
In this section, i corresponds to the chip-select number, i = 0 to 6.
Table 7-54. GPMC Registers
Address Offset Register Name Section
0h GPMC_REVISION Section 7.1.5.1
10h GPMC_SYSCONFIG Section 7.1.5.2
14h GPMC_SYSSTATUS Section 7.1.5.3
18h GPMC_IRQSTATUS Section 7.1.5.4
1Ch GPMC_IRQENABLE Section 7.1.5.5
40h GPMC_TIMEOUT_CONTROL Section 7.1.5.6
44h GPMC_ERR_ADDRESS Section 7.1.5.7
48h GPMC_ERR_TYPE Section 7.1.5.8
50h GPMC_CONFIG Section 7.1.5.9
54h GPMC_STATUS Section 7.1.5.10
60h + (30h × i) GPMC_CONFIG1_i
(1)
Section 7.1.5.11
64h + (30h × i) GPMC_CONFIG2_i
(1)
Section 7.1.5.12
68h + (30h × i) GPMC_CONFIG3_i
(1)
Section 7.1.5.13
6Ch + (30h × i) GPMC_CONFIG4_i
(1)
Section 7.1.5.14
70h + (30h × i) GPMC_CONFIG5_i
(1)
Section 7.1.5.15
74h + (30h × i) GPMC_CONFIG6_i
(1)
Section 7.1.5.16
78h + (30h × i) GPMC_CONFIG7_i
(1)
Section 7.1.5.17
7Ch + (30h × i) GPMC_NAND_COMMAND_i
(1)
Section 7.1.5.18
80h + (30h × i) GPMC_NAND_ADDRESS_i
(1)
Section 7.1.5.19
84h + (30h × i) GPMC_NAND_DATA_i
(1)
Section 7.1.5.20
1E0h GPMC_PREFETCH_CONFIG1 Section 7.1.5.21
1E4h GPMC_PREFETCH_CONFIG2 Section 7.1.5.22
1ECh GPMC_PREFETCH_CONTROL Section 7.1.5.23
1F0h GPMC_PREFETCH_STATUS Section 7.1.5.24
1F4h GPMC_ECC_CONFIG Section 7.1.5.25
1F8h GPMC_ECC_CONTROL Section 7.1.5.26
1FCh GPMC_ECC_SIZE_CONFIG Section 7.1.5.27
200h + (4h × k) GPMC_ECCj_RESULT
(2)(3)
Section 7.1.5.28
240h + (10h × i) GPMC_BCH_RESULT0_i
(1)
Section 7.1.5.29
244h + (10h × i) GPMC_BCH_RESULT1_i
(1)
Section 7.1.5.30
248h + (10h × i) GPMC_BCH_RESULT2_i
(1)
Section 7.1.5.31
24Ch + (10h × i) GPMC_BCH_RESULT3_i
(1)
Section 7.1.5.32
300h + (10h × i) GPMC_BCH_RESULT4_i
(1)
Section 7.1.5.34
304h + (10h × i) GPMC_BCH_RESULT5_i
(1)
Section 7.1.5.35
308h + (10h × i) GPMC_BCH_RESULT6_i
(1)
Section 7.1.5.36
2D0h GPMC_BCH_SWDATA Section 7.1.5.33
(1)
i = 0 to 6 for GPMC
(2)
j = 1 to 9 for GPMC
(3)
k = j - 1
366
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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