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Interrupt Controller Registers
6.5.1.36 INTC_ITR3 Register (offset = E0h) [reset = 0h]
INTC_ITR3 is shown in Figure 6-39 and described in Table 6-39.
This register shows the raw interrupt input status before masking
Figure 6-39. INTC_ITR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Itr
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-39. INTC_ITR3 Register Field Descriptions
Bit Field Type Reset Description
31-0 Itr R 0h
Interrupt status before masking
241
SPRUH73H–October 2011–Revised April 2013 Interrupts
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