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Enhanced PWM (ePWM) Module
15.2.4.5.5 Trip-Zone Clear Register (TZCLR)
The trip-zone clear register (TZCLR) is shown in Figure 15-89 and described in Table 15-83.
Figure 15-89. Trip-Zone Clear Register (TZCLR)
15 3 2 1 0
Reserved OST CBC INT
R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-83. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bits Name Value Description
15-3 Reserved 0 Reserved
2 OST Clear Flag for One-Shot Trip (OST) Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
1 CBC Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
0 INT Global Interrupt Clear Flag
0 Has no effect. Always reads back a 0.
1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the TZFLG[INT]
bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated.
Clearing all flag bits will prevent further interrupts.
15.2.4.5.6 Trip-Zone Force Register (TZFRC)
The trip-zone force register (TZFRC) is shown in Figure 15-90 and described in Table 15-84.
Figure 15-90. Trip-Zone Force Register (TZFRC)
15 3 2 1 0
Reserved OST CBC Rsvd
R-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-84. Trip-Zone Force Register (TZFRC) Field Descriptions
Bits Name Value Description
15-3 Reserved 0 Reserved
2 OST Force a One-Shot Trip Event via Software
0 Writing of 0 is ignored. Always reads back a 0.
1 Forces a one-shot trip event and sets the TZFLG[OST] bit.
1 CBC Force a Cycle-by-Cycle Trip Event via Software
0 Writing of 0 is ignored. Always reads back a 0.
1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
0 Reserved 0 Reserved
1599
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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