Texas Instruments AM335 Series Technical Reference Manual

www.ti.com Enhanced PWM (ePWM) Module
15.2.4.6.5 Event-Trigger Force Register (ETFRC)
The event-trigger force register (ETFRC) is shown in Figure 15-95 and described in Table 15-90.
Figure 15-95. Event-Trigger Force Register (ETFRC)
15 1 0
Reserved INT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 15-90. Event-Trigger Force Register (ETFRC) Field Descriptions
Bits Name Value Description
15-1 Reserved 0 Reserved
0 INT INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The
INT flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
1603
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English