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7.3.6.11 DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-138. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-40h R-0h
15 10 9 0
Reserved WR_DATA_SLAVE_RATIO_CS0
R-0h W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-161. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 40h Reserved
19-10 Reserved 0
9-0 WR_DATA_SLAVE_RATIO_CS0 40h Ratio value for write data slave DLL for CS0.
This is the fraction of a clock cycle represented by the shift to be applied to
the write DQ muxes in units of 256ths. In other words, the full-cycle tap
value from the master DLL will be scaled by this number over 256 to get the
delay value for the slave delay line.
474
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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