McASP Registers
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22.4.1.13 Receiver Global Control Register (RGBLCTL)
Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL)
affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL.
RGBLCTL allows the receiver to be reset independently from the transmitter. The RGBLCTL is shown in
Figure 22-51 and described in Table 22-24. See Section 22.4.1.9 for a detailed description of GBLCTL.
Figure 22-51. Receiver Global Control Register (RGBLCTL)
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved XFRST XSMRST XSRCLR XHCLKRST XCLKRST
R-0 R-0 R-0 R-0 R-0 R-0
7 5 4 3 2 1 0
Reserved RFRST RSMRST RSRCLR RHCLKRST RCLKRST
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-24. Receiver Global Control Register (RGBLCTL) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
12 XFRST x Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of
GBLCTL. Writes have no effect.
11 XSMRST x Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL.
Writes have no effect.
10 XSRCLR x Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes
have no effect.
9 XHCLKRST x Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit
value of GBLCTL. Writes have no effect.
8 XCLKRST x Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL.
Writes have no effect.
7-5 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
4 RFRST Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL.
0 Receive frame sync generator is reset.
1 Receive frame sync generator is active.
3 RSMRST Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL.
0 Receive state machine is held in reset.
1 Receive state machine is released from reset.
2 RSRCLR Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL.
0 Receive serializers are cleared.
1 Receive serializers are active.
1 RHCLKRST Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of
GBLCTL.
0 Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1.
1 Receive high-frequency clock divider is running.
0 RCLKRST Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL.
0 Receive clock divider is held in reset.
1 Receive clock divider is running.
3848
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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