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DCAN Registers
23.4.7 PERR Register (offset = 1Ch) [reset = 0h]
PERR is shown in Figure 23-25 and described in Table 23-20.
If a parity error is detected, the PER flag will be set in the error and status register. This bit is not reset by
the parity check mechanism; it must be reset by reading the error and status register. In addition to the
PER flag, the parity error code register will indicate the memory area where the parity error has been
detected (message number and word number). If more than one word with a parity error was detected, the
highest word number with a parity error will be displayed. After a parity error has been detected, the
register will hold the last error code until power is removed.
Figure 23-25. PERR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Word_Number
R-0h R-0h
7 6 5 4 3 2 1 0
Message_Number
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-20. PERR Register Field Descriptions
Bit Field Type Reset Description
31-11 Reserved R 0h
10-8 Word_Number R 0h
Word number where parity error has been detected.
0x01 to 0x05 = RDA word number (1 to 5) of the message object
(according to the message RAM representation in RDA mode).
7-0 Message_Number R 0h
Message number.
0x01 to 0x80 = Message object number where parity error has been
detected
3933
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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