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GPMC
7.1.3.3.7 GPMC Address and Data Bus
The current application supports GPMC connection to NAND devices and to address/data-multiplexed
memories or devices. Connection to address/data-nonmultiplexed memories Depending on the GPMC
configuration of each chip-select, address and data bus lines that are not required for a particular access
protocol are not updated (changed from current value) and are not sampled when input (input data bus).
• For address/data-multiplexed and AAD-multiplexed NOR devices, the address is multiplexed on the
data bus.
• 8-bit wide NOR devices do not use GPMC I/O: GPMC_AD[15-8] for data (they are used for address if
needed).
• 16-bit wide NAND devices do not use GPMC I/O: GPMC_A[27-0].
• 8-bit wide NAND devices do not use GPMC I/O: GPMC_A[27-0] and GPMC I/O: GPMC_AD[15-8].
7.1.3.3.7.1 GPMC I/O Configuration Setting
NOTE: In this section and next sections, the i in GPMC_CONFIGx_i stands for the GPMC chip-
select i where i = 0 to 6.
To select a NAND device, program the following register fields:
• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 10b
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 00
To select an address/data-multiplexed device, program the following register fields:
• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 00
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 10b
To select an address/address/data-multiplexed device, program the following register fields:
• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 00
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 01b
To select an address/data-nonmultiplexed device , program the following register fields:
• GPMC_CONFIG1_i[11-10] DEVICETYPE field = 00
• GPMC_CONFIG1_i[9-8] MUXADDDATA bit = 00
7.1.3.3.8 Address Decoder and Chip-Select Configuration
Addresses are decoded accordingly with the address request of the chip-select and the content of the
chip-select base address register file, which includes a set of global GPMC configuration registers and
eight sets of chip-select configuration registers.
The GPMC configuration register file is memory-mapped and can be read or written with byte, 16-bit word,
or 32-bit word accesses. The register file should be configured as a noncacheable, nonbufferable region
to prevent any desynchronization between host execution (write request) and the completion of register
configuration (write completed with register updated). Section 7.1.5 provides the GPMC register locations.
For the map of GPMC memory locations, see Table 7-54.
After the chip-select is configured, the access engine accesses the external device, drives the external
interface control signals, and applies the interface protocol based on user-defined timing parameters and
settings.
263
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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