Functional Description
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24.3.2.10 FIFO Buffer Management
The McSPI controller has a built-in 64-byte buffer in order to unload DMA or interrupt handler and improve
data throughput.
This buffer can be used by only one channel and is selected by setting MCSPI_CH(I)CONF[FFER] and/or
MCSPI_CH(I)CONF[FFEW] to 1.
If several channels are selected and several FIFO enable bit fields set to 1, the controller forces the buffer
to be disabled for all channels. It is the responsibility of the driver to enable the buffer for only one
channel.
The buffer can be used in the modes defined below:
• Master or Slave mode.
• Transmit only, Receive only or Transmit/Receive mode.
• Single channel or turbo mode, or in normal round robin mode. In round robin mode the buffer is used
by only one channel.
• All word length MCSPI_CH(I)CONF[WL] are supported.
Two levels AEL and AFL located in MCSPI_XFERLEVEL register rule the buffer management. The
granularity of these levels is one byte, then it is not aligned with SPI word length. It is the responsibility of
the driver to set these values as a multiple of SPI word length defined in MCSPI_CH(I)CONF[WL]. The
number of byte written in the FIFO depends on word length (see Table 24-9).
Table 24-9. FIFO Writes, Word Length Relationship
SPI Word Length WL
3 ≤ WL ≤ 7 8 ≤ WL ≤ 15 16 ≤ WL ≤ 31
Number of byte written in the FIFO 1 byte 2 bytes 4 byte
24.3.2.10.1 Split FIFO
The FIFO can be split into two part when module is configured in transmit/receive mode
MCSPI_CH(I)CONF[TRM] is cleared to 0 and MCSPI_CH(I)CONF[FFER] and MCSPI_CH(I)CONF[FFEW]
asserted. Then system can access a 32-byte depth FIFO per direction.
The FIFO buffer pointers are reset when the corresponding channel is enabled or FIFO configuration
changes.
4014
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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