TX Register
RX Register
FIFO
64-Byte
Depth
TX Shift Register
RX Shift Register
TX Shift Clock
RX Shift Clock
SPI Domain
OCP Domain
Configuration:
MCSPI_CH(i)CONF[TRM]=0x0 Transmit/receive mode
MCSPI_CH(i)CONF[FFRE]=0x1 FIFO enabled on receive path
MCSPI_CH(i)CONF[FFWE]=0x0 FIFO disabled on transmit path
OCP Bus
SPIDATAO
SPIDATAI
TX Register
RX Register
FIFO
64-Byte
Depth
TX Shift Register
RX Shift Register
TX Shift Clock
RX Shift Clock
SPI Domain
OCP Domain
Configuration:
MCSPI_CH(i)CONF[TRM]=0x0 Transmit/receive mode
MCSPI_CH(i)CONF[FFRE]=0x0 FIFO disabled on receive path
MCSPI_CH(i)CONF[FFWE]=0x0 FIFO disabled on transmit path
OCP Bus
SPIDATAO
SPIDATAI
www.ti.com
Functional Description
Figure 24-13. Transmit/Receive Mode With No FIFO Used
Figure 24-14. Transmit/Receive Mode With Only Receive FIFO Enabled
4015
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
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