TX Register
RX Register
FIFO
32-Byte
Depth
TX Shift Register
RX Shift Register
TX Shift Clock
RX Shift Clock
SPI Domain
OCP Domain
Configuration:
MCSPI_CH(i)CONF[TRM]=0x0 Transmit/receive mode
MCSPI_CH(i)CONF[FFRE]=0x1 FIFO enabled on receive path
MCSPI_CH(i)CONF[FFWE]=0x0 FIFO disabled on transmit path
OCP Bus
SPIDATAO
SPIDATAI
FIFO
32-Byte
Depth
TX Register
RX Register
FIFO
64-Byte
Depth
TX Shift Register
RX Shift Register
TX Shift Clock
RX Shift Clock
SPI Domain
OCP Domain
Configuration:
MCSPI_CH(i)CONF[TRM]=0x0 Transmit/receive mode
MCSPI_CH(i)CONF[FFRE]=0x0 FIFO disabled on receive path
MCSPI_CH(i)CONF[FFWE]=0x1 FIFO enabled on transmit path
OCP Bus
SPIDATAO
SPIDATAI
Functional Description
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Figure 24-15. Transmit/Receive Mode With Only Transmit FIFO Used
Figure 24-16. Transmit/Receive Mode With Both FIFO Direction Used
4016
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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