www.ti.com
DMTimer
20.1.5.14 TMAR Register (offset = 4Ch) [reset = 0h]
TMAR is shown in Figure 20-22 and described in Table 20-24.
The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter s
current value with the value stored in the TMAR register.
Figure 20-22. TMAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPARE_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-24. TMAR Register Field Descriptions
Bit Field Type Reset Description
31-0 COMPARE_VALUE R/W 0h
Value to be compared to the timer counter
3581
SPRUH73H–October 2011–Revised April 2013 Timers
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
