DCAN Registers
www.ti.com
23.4.24 MSGVAL_X Register (offset = C0h) [reset = 0h]
MSGVAL_X is shown in Figure 23-42 and described in Table 23-37.
With the message valid X register, the CPU can detect if one or more bits in the different message valid
registers are set. Each bit of this register represents a group of eight message objects. If at least one of
the MsgVal bits of these message objects are set, the corresponding bit in the message valid X register
will be set. Example 3. Bit 0 of the message valid X register represents byte 0 of the message valid 1
register. If one or more bits in this byte are set, bit 0 of the message valid X register will be set.
Figure 23-42. MSGVAL_X Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
MsgValReg8 MsgValReg7 MsgValReg6 MsgValReg5
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
MsgValReg4 MsgValReg3 MsgValReg2 MsgValReg1
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-37. MSGVAL_X Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-14 MsgValReg8 R 0h
MsgValReg8
13-12 MsgValReg7 R 0h
MsgValReg7
11-10 MsgValReg6 R 0h
MsgValReg6
9-8 MsgValReg5 R 0h
MsgValReg5
7-6 MsgValReg4 R 0h
MsgValReg4
5-4 MsgValReg3 R 0h
MsgValReg3
3-2 MsgValReg2 R 0h
MsgValReg2
1-0 MsgValReg1 R 0h
MsgValReg1
3950
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
