AFSX
pin
10
1 0
Transmit frame sync
generator
generator
Receive frame sync
XCLK RCLK
0
1
FSXP
FSXM
(internal/
external)
Internal
frame
sync
pin
AFSR
FSRP
0
1
0
1
1
0
FSRM
(internal/external)
(AFSRCTL.1)
ASYNC
FSRP
sync
frame
Internal0
1
(AFSXCTL.0)
XMOD (AFSXCTL[15-7])
FXWID (AFSXCTL.4)
RMOD (AFSRCTL[15-7])
FRWID (AFSRCTL.4)
(AFSRCTL.0)
(ACLKXCTL.6)
(AFSXCTL.1)
(AFSRCTL.0)
FSXP
(AFSXCTL.0)
Functional Description
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22.3.5.3 Frame Sync Generator
There are two different modes for frame sync: burst and TDM. A block diagram of the frame sync
generator is shown in Figure 22-19. The frame sync options are programmed by the receive and transmit
frame sync control registers (AFSRCTL and AFSXCTL). The options are:
• Internally-generated or externally-generated.
• Frame sync polarity: rising edge or falling edge.
• Frame sync width: single bit or single word.
• Bit delay: 0, 1, or 2 cycles before the first data bit.
The transmit frame sync pin is AFSX and the receive frame sync pin is AFSR. A typical usage for these
pins is to carry the left/right clock (LRCLK) signal when transmitting and receiving stereo data.
Regardless if the AFSX/AFSR is internally generated or externally sourced, the polarity of AFSX/AFSR is
determined by FSXP/FSRP, respectively, to be either rising or falling edge. If FSXP/FSRP = 0, the frame
sync polarity is rising edge. If FSRP/FSRP = 1, the frame sync polarity is falling edge.
Figure 22-19. Frame Sync Generator Block Diagram
3786
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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