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UART Registers
19.5.1.49 IER2 Register
The IER2 register enables RX/TX FIFOs empty corresponding interrupts. The IER2 register (IER2) is
shown in Figure 19-82 and described in Table 19-81.
Figure 19-82. IER2 Register
31 2 1 0
Reserved EN_TXFIFO_E EN_RXFIFO_E
MPTY MPTY
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-81. IER2 Register Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved.
1 EN_TXFIFO_EM 0 Disables EN_TXFIFO_EMPTY interrupt.
PTY
1 Enables EN_TXFIFO_EMPTY interrupt.
0 EN_RXFIFO_EM Number of bits by characters.
PTY
0 Disables EN_RXFIFO_EMPTY interrupt.
1 Enables EN_RXFIFO_EMPTY interrupt.
3545
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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