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Ethernet Subsystem Registers
14.5.6.7 P0_CPDMA_TX_PRI_MAP Register (offset = 1Ch) [reset = 76543210h]
P0_CPDMA_TX_PRI_MAP is shown in Figure 14-127 and described in Table 14-142.
CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY
Figure 14-127. P0_CPDMA_TX_PRI_MAP Register
31 30 29 28 27 26 25 24
Reserved PRI7 Reserved PRI6
R/W-7h R/W-6h
23 22 21 20 19 18 17 16
Reserved PRI5 Reserved PRI4
R/W-5h R/W-4h
15 14 13 12 11 10 9 8
Reserved PRI3 Reserved PRI2
R/W-3h R/W-2h
7 6 5 4 3 2 1 0
Reserved PRI1 Reserved PRI0
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-142. P0_CPDMA_TX_PRI_MAP Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI7 R/W 7h Priority
7 - A packet pri of 0x7 is mapped (changed) to this header packet
pri.
26-24 PRI6 R/W 6h Priority
6 - A packet pri of 0x6 is mapped (changed) to this header packet
pri.
22-20 PRI5 R/W 5h Priority
5 - A packet pri of 0x5 is mapped (changed) to this header packet
pri.
18-16 PRI4 R/W 4h Priority
4 - A packet pri of 0x4 is mapped (changed) to this header packet
pri.
14-12 PRI3 R/W 3h Priority
3 - A packet pri of 0x3 is mapped (changed) to this header packet
pri.
10-8 PRI2 R/W 2h Priority
2 - A packet pri of 0x2 is mapped (changed) to this header packet
pri.
6-4 PRI1 R/W 1h Priority
1 - A packet pri of 0x1 is mapped (changed) to this header packet
pri.
2-0 PRI0 R/W 0h Priority
0 - A packet pri of 0x0 is mapped (changed) to this header packet
pri.
1363
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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