www.ti.com
Interrupt Controller Registers
6.5.1.38 INTC_MIR_CLEAR3 Register (offset = E8h) [reset = 0h]
INTC_MIR_CLEAR3 is shown in Figure 6-41 and described in Table 6-41.
This register is used to clear the interrupt mask bits.
Figure 6-41. INTC_MIR_CLEAR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MirClear
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-41. INTC_MIR_CLEAR3 Register Field Descriptions
Bit Field Type Reset Description
31-0 MirClear W 0h
Write 1 clears the mask bit to 0, reads return 0
243
SPRUH73H–October 2011–Revised April 2013 Interrupts
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
