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14.2.2 Ethernet Switch Clock and Reset Management
The ethernet switch controller operates in its own clock domain and its initiator and target interfaces are
connected to the L3/L4 through asynchronous bridges. The OCP interfaces are driven by the MAIN clock
input. Additional reference clock inputs are provided for operating the various ethernet ports at different
rates.
Table 14-3. Ethernet Switch Clock Signals
Clock Signal Max Freq Reference / Source Comments
rft_clk 125 MHz Tied low not supported
Gigabit GMII Tx Reference
clock
main_clk 125 MHz CORE_CLKOUTM5 / 2 pd_per_cpsw_125mhz_gclk
Logic/Interface clock from PRCM
mhz250_clk 250 MHz CORE_CLKOUTM5 pd_per_cpsw_250mhz_gclk
Gigabit RGMII Reference clock from PRCM
mhz50_clk 50 MHz CORE_CLKOUTM5 / 5 pd_per_cpsw_50mhz_gclk
RMII and 100mbps RGMII from PRCM
Reference clock
mhz5_clk 5 MHz CORE_CLKOUTM5 / 50 pd_per_cpsw_5mhz_gclk
10 mbpsRGMII Reference from PRCM
clock
cpts_rft_clk 250 MHz CORE_CLKOUTM4 pd_per_cpsw_cpts_rft_clk
IEEE 1588v2 clock CORE_CLKOUTM5 from PRCM
gmii1_mr_clk 25 MHz External Pin gmii1_rxclk_in
GMII Port 1 Receive clock from GMII1_RCLK pad
gmii2_mr_clk 25 MHz External Pin gmii2_rxclk_in
GMII Port 2 Receive clock from GMII2_RCLK pad
gmii1_mt_clk 25 MHz External Pin gmii1_txclk_in
GMII Port 1 Transmit clock from GMII1_TCLK pad
gmii2_mt_clk 25 MHz External Pin gmii2_txclk_in
GMII Port 2 Transmit clock from GMII2_TCLK pad
rgmii1_rxc_clk 250 MHz External Pin rgmii1_rclk_in
RGMII Port 1 Receive clock from RGMII1_RCLK pad
rgmii2_rxc_clk 250 MHz External Pin rgmii2_rclk_in
RGMII Port 2 Receive clock from RGMII2_RCLK pad
rmii1_mhz_50_clk 50 MHz External Pin rmii1_refclk_in
RMII Port 1 Reference clock from RMII1_REFCLK pad
rmii2_mhz_50_clk 50 MHz External Pin rmii2_refclk_in
RMII Port 2 Reference clock from RMII2_REFCLK pad
1168
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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