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CONTROL_MODULE Registers
9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h]
mpuss_hw_dbg_info is shown in Figure 9-44 and described in Table 9-51.
Figure 9-44. mpuss_hw_dbg_info Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hw_dbg_info
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-51. mpuss_hw_dbg_info Register Field Descriptions
Bit Field Type Reset Description
31-0 hw_dbg_info R 0h Hardware Debug Info from MPU.
805
SPRUH73H–October 2011–Revised April 2013 Control Module
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