USB Registers
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16.5.1.23 IRQDMAENABLE0 Register (offset = 140h) [reset = 0h]
IRQDMAENABLE0 is shown in Figure 16-44 and described in Table 16-52.
Figure 16-44. IRQDMAENABLE0 Register
31 30 29 28 27 26 25 24
DMA_EN_RX0_15 Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved DMA_EN_RX0_1 Reserved
R/W-0h
15 14 13 12 11 10 9 8
DMA_EN_TX0_15 Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved DMA_EN_TX0_2 Reserved DMA_EN_TX0_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-52. IRQDMAENABLE0 Register Field Descriptions
Bit Field Type Reset Description
31 DMA_EN_RX0_15 R/W 0h DMA threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint
15.
...
...
...
...
...
17 DMA_EN_RX0_1 R/W 0h DMA threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint 1.
15 DMA_EN_TX0_15 R/W 0h DMA threshold enable value for tx_pkt_cmp_0 for USB0 Endpoint
15.
...
...
...
...
...
2 DMA_EN_TX0_2 R/W 0h DMA threshold enable value for tx_pkt_cmp_0 for USB0 Endpoint 2.
0 DMA_EN_TX0_1 R/W 0h DMA threshold enable value for tx_pkt_cmp_0 for USB0 Endpoint 1.
1784
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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