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DCAN Registers
23.4.45 IF3OBS Register (offset = 140h) [reset = 0h]
IF3OBS is shown in Figure 23-63 and described in Table 23-58.
The IF3 register set can automatically be updated with received message objects without the need to
initiate the transfer from message RAM by CPU. The observation flags (Bits [4:0]) in the IF3 observation
register are used to determine, which data sections of the IF3 interface register set have to be read in
order to complete a DMA read cycle. After all marked data sections are read, the DCAN is enabled to
update the IF3 interface register set with new data. Any access order of single bytes or half-words is
supported. When using byte or half-word accesses, a data section is marked as completed, if all bytes are
read. Note: If IF3 Update Enable is used and no Observation flag is set, the corresponding message
objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read
accesses. A write access to this register aborts a pending DMA cycle by resetting the DMA line and
enables updating of IF3 interface register set with new data. To avoid data inconsistency, the DMA
controller should be disabled before reconfiguring IF3 observation register. The status of the current read-
cycle can be observed via status flags (Bits [12:8]). If an interrupt line is available for IF3, an interrupt will
be generated by IF3Upd flag. See the device-specific data sheet for the availability of this interrupt source.
With this interrupt, the observation status bits and the IF3Upd bit could be used by the application to
realize the notification about new IF3 content in polling or interrupt mode.
Figure 23-63. IF3OBS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
IF3_Upd Reserved IF3_SDB IF3_SDA IF3_SC IF3_SA IF3_SM
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved DataB DataA Ctrl Arb Mask
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-58. IF3OBS Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 IF3_Upd R 0h
IF3 Update Data
0x0 = No new data has been loaded since last IF3 read.
0x1 = New data has been loaded since last IF3 read.
14-13 Reserved R 0h
12 IF3_SDB R 0h
IF3 Status of Data B read access
0x0 = All Data B bytes are already read out, or are not marked to be
read.
0x1 = Data B section has still data to be read out.
11 IF3_SDA R 0h
IF3 Status of Data A read access
0x0 = All Data A bytes are already read out, or are not marked to be
read.
0x1 = Data A section has still data to be read out.
10 IF3_SC R 0h
IF3 Status of control bits read access
0x0 = All control section bytes are already read out, or are not
marked to be read.
0x1 = Control section has still data to be read out.
3977
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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