DMTimer 1ms
www.ti.com
20.2.5.20 TOWR Register (offset = 58h) [reset = 0h]
TOWR is shown in Figure 20-54 and described in Table 20-55.
This register holds the number of masked overflow interrupts.
Figure 20-54. TOWR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
OVF_WRAPPING_VALUE
R/W-0h
15 14 13 12 11 10 9 8
OVF_WRAPPING_VALUE
R/W-0h
7 6 5 4 3 2 1 0
OVF_WRAPPING_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-55. TOWR Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R 0h
Reads return 0
23-0 OVF_WRAPPING_VALU R/W 0h
The number of masked interrupts.
E
3620
Timers SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
