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Table 7-107. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=3 and
REG_EBANK_POS=1 (continued)
Logical Address
Chip Select Bank Address Row Address Column Address
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Since the DDR2/3/mDDR memory controller interleaves among less number of banks when
IBANK_POS!= 0 or EBANK_POS= 1, these cases are lower in performance than the IBANK_POS= 0
case. Thus these cases are only recommended to be used along with partial array self-refresh where
performance can be traded off for power savings.
7.3.3.5 Performance Management
7.3.3.5.1 Command Ordering and Scheduling
The DDR2/3/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/3/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
The DDR2/3/mDDR memory controller examines all the commands stored in the command FIFO to
schedule commands to the external memory. All commands from same master will complete in order,
regardless of the master priority. The memory controller does not guarantee ordering between commands
from different masters. However, the memory controller will maintain data coherency. Therefore, the
memory controller will block a command, regardless of master priority, if that command is to the same
block address (2048 bytes) as an older command. Thus, the memory controller might have one or more
pending read or write for each master. Among all pending reads, the memory controller selects all reads
that have their corresponding SDRAM banks already open. Similarly, among all pending writes, the
memory controller selects all writes that have their corresponding SDRAM banks already open.
As a result of the above reordering, at any point of time the memory controller might have several pending
reads and writes that have their corresponding banks open. The memory controller then selects the
highest priority read from pending reads, and the highest priority write from pending writes. If two or more
commands have the highest priority, the memory controller selects the oldest command. As a result, the
memory controller might now have a final read and a final write command. The memory controller will pick
either the read or the write command depending on the value programmed in the Read Write Execution
Threshold register. The memory controller will keep executing reads until the read threshold is met and
then switch to executing writes. The memory controller will then keep executing writes until the write
threshold is met and then switch back to executing reads. The memory controller will satisfy meeting the
threshold values only if that type of command is available for execution, otherwise it will switch to the other
type. Similarly, the memory controller will satisfy meeting the threshold value only if the FIFOs for that type
have space (Read Data FIFO for reads and Write Status FIFO for writes), otherwise it will switch to the
other type.
The memory controller completes executing an OCP command before it switches to another command.
All the accesses to an SDRAM are pipe-lined to maximize the external bus utilization. In other words
accesses to an SDRAM are issued back to back such that there are minimum idle cycles between any two
accesses. This includes the scheduling listed above to minimize the overhead of opening and closing of
SDRAM banks. All of these is done while fulfilling the access timing requirements of an SDRAM.
Besides commands received from on-chip resources, the DDR2/3/mDDR memory controller also issues
refresh commands. The DDR2/3/mDDR memory controller attempts to delay refresh commands as long
as possible to maximize performance while meeting the SDRAM refresh requirements. As the
DDR2/3/mDDR memory controller issues read, write, and refresh commands to DDR2/3/mDDR SDRAM
device, it follows the following priority scheme:
1. (Highest priority) SDRAM refresh request due to Refresh Must level of refresh urgency reached (see
Section 7.3.3.5.5).
414
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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