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WATCHDOG
20.4.4.1.2 WDT_WDSC Register (offset = 10h) [reset = 10h]
WDT_WDSC is shown in Figure 20-100 and described in Table 20-113.
The Watchdog System Control Register controls the various parameters of the L4 interface.
Figure 20-100. WDT_WDSC Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved EMUFREE IDLEMODE Reserved SOFTRESET Reserved
R-0h R/W-0h R/W-2h R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-113. WDT_WDSC Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5 EMUFREE R/W 0h
Emulation mode
0x0 = Timer counter frozen in emulation
0x1 = Timer counter free-running in emulation
4-3 IDLEMODE R/W 2h
Configuration of the local target state management mode.By
definition, target can handle read/write transaction as long as it is out
of IDLE state.
0x0 = Force-idle mode: local target's idle state follows
(acknowledges) the system's idle requests unconditionally, i.e.
regardless of the IP module's internal requirements. Backup mode,
for debug only.
0x1 = No-idle mode: local target never enters idle state.Backup
mode, for debug only.
0x2 = Smart-idle mode: local target's idle state eventually follows
(acknowledges) the system's idle requests, depending on the IP
module's internal requirements. IP module shall not generate (IRQ-
or DMA-request-related) wakeup events.
0x3 = Smart-idle wakeup-capable mode: local target's idle state
eventually follows (acknowledges) the system's idle requests,
depending on the IP module's internal requirements. IP module may
generate (IRQ- or DMA-request-related) wakeup events when in idle
state.
2 Reserved R 0h
1 SOFTRESET R/W 0h Software reset.
(Optional)
0x0x0(W) = No action
0x0x0(R) = Reset done, no pending action
0x0x1(W) = Initiate software reset.
0x0x1(R) = Reset (software or other) ongoing
0 Reserved R 0h
3683
SPRUH73H–October 2011–Revised April 2013 Timers
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