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EDMA3 Registers
11.4.1.1.3 EDMA3CC System Configuration Register (SYSCONFIG)
The EDMA3CC system configuration register is used for clock management configuration. The register is
shown in Figure 11-44 and described in Table 11-28.
Figure 11-44. EDMA3CC System Configuration Register (SYSCONFIG)
31 16
Reserved
R-0
15 6 5 4 3 2 1 0
Reserved Reserved IDLEMODE Reserved Reserved
R-0 R-0 R/W-2 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-28. EDMA3CC System Configuration Register (SYSCONFIG) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Read returns 0.
5-4 Reserved 0 Reserved.
3-2 IDLEMODE 2h Configuration of the local target state management mode. By definition, target can handle
read/write transaction as long as it is out of IDLE state.
0x0 = Force-idle mode: local target's idle state follows (acknowledges) the system's idle
requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup
mode, for debug only.
0x1 = No-idle mode: local target never enters idle state. Backup mode, for debug only.
0x2 = Smart-idle mode: local target's idle state eventually follows (acknowledges) the
system's idle requests, depending on the IP module's internal requirements. IP module
shall not generate (IRQ- or DMA-request-related) wakeup events.
0x3 = Reserved.
1 Reserved 0 Reserved.
0 Reserved 0 Reserved.
945
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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